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71	Hybrid Scheduling for Realistic Image Synthesis Erik Reinhard1 Alan Chalmers1 Frederik W. Jansen2 Abstract Rendering a single high quality image may take several hours, or even days. The complexity of both the model and Add to Reading List Source URL: www.cg.its.tudelft.nl Language: English - Date: 2007-08-03 10:27:48 Parallel computing 3D rendering 3D computer graphics Global illumination algorithms Cache Rendering Ray tracing Cache algorithms Data Ray-tracing hardware CPU cache
72	On p-Kernel Construction Jochen GMD Add to Reading List Source URL: www.eecs.harvard.edu Language: English Central processing unit Operating system kernels Computer memory Virtual memory Monolithic kernels Mach Translation lookaside buffer Kernel Thread Linux kernel CPU cache Architecture of Windows NT
73	Cosmic Microwave Background Map-Making at the Petascale and Beyond Rajesh Sudarsan Julian Borrill Christopher Cantalupo Theodore Kisner Kamesh Madduri Leonid Oliker Horst Simon Yili Zheng Computational Research Division, Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-07-16 16:52:53 Parallel computing Supercomputers Multi-core processor Opteron CPU cache Cray Cosmic microwave background Pleiades Jaguar OpenMP Message Passing Interface
74	Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-11-03 08:27:59 Computer memory Transaction processing Parallel computing Compiler construction Concurrency Cache coherence Memory ordering Consistency model Linearizability Sequential consistency CPU cache Processor consistency
75	MASC: Ultra-Low Energy Multiple-Access SingleCharge TCAM for Approximate Computing Mohsen Imani, Shruti Patil, Tajana S. Rosing CSE Department, University of California San Diego, La Jolla, CA 92093, USA {moimani, patil, Add to Reading List Source URL: moimani.weebly.com Language: English - Date: 2016-05-07 11:51:12 Computer memory Associative arrays Emerging technologies Computer networking Content-addressable memory CPU cache General-purpose computing on graphics processing units Lookup table Sense amplifier Memristor
76	Improving the Performance of MPI Derived Datatypes by Optimizing Memory-Access Cost Surendra Byna† † William Gropp‡ Add to Reading List Source URL: wgropp.cs.illinois.edu Language: English - Date: 2016-08-16 11:52:12 Compiler optimizations Central processing unit Computer memory Compiler construction Computer architecture Message Passing Interface CPU cache MPICH Cache Data structure alignment Automatically Tuned Linear Algebra Software Optimizing compiler
77	Resource-Efficient, Hierarchical Auto-Tuning of a Hybrid Lattice Boltzmann Computation on the Cray XT4 Samuel Williams? , Jonathan Carter? , Leonid Oliker? John Shalf? , Katherine Yelick?† ? CRD/NERSC, Lawrence Berkele Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:52:12 Parallel computing Thread Multithreading Multi-core processor Task parallelism SPMD CPU cache Cell Message Passing Interface Algorithmic skeleton
78	Forecasting the cost of processing multi-join queries via hashing for main-memory databases Add to Reading List Source URL: web.cse.ohio-state.edu Language: English - Date: 2015-08-14 19:41:23 Search algorithms Hashing Cache Arrays Hash table Hash join Hash function CPU cache Query optimization Trie Join Database
79	multicore-panel-final.ppt Add to Reading List Source URL: wgropp.cs.illinois.edu Language: English - Date: 2016-08-16 11:52:11 Parallel computing Multi-core processor CPU cache Thread Xeon Phi Message Passing Interface
80	EUROPEAN PATENT OFFICE U.S. PATENT AND TRADEMARK OFFICE CPC NOTICE OF CHANGES 266 DATE: AUGUST 1, 2016 PROJECT RP0311 Add to Reading List Source URL: www.cooperativepatentclassification.org Language: English Cache Central processing unit Computer memory CPU cache Web cache Trie Draft:Cache memory

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